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#219: Back to Basics: Introduction to Field Effect Transistors J…

#219: Back to Basics: Introduction to Field Effect Transistors J...

A basic introduction to the Field Effect Transistor (FET). This includes a basic description of the Junction FET (JFET) and the Metal Oxide FET (MOSFET), and also discusses N-Channel vs. P-Channel, as well as Depletion Mode and Enhancement Mode type devices. The function of the Gate, Source and Drain terminals are reviewed. The linear region and saturation region of operation of the devices is described and demonstrated. In a short video like this, it is impossible to get into depth in any application - the intent with this video is to lay the foundation of the operation of the FET and to make sense of the various terminology surrounding the different types of devices. The notes from this video can be found here:


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  1. Date: December 31, 2016 at 17:14
    Author: Dathan Walters

    A Transistor inverters the polarity of the input signal on the collector while a FET's drain doesn't inverter the input signal. Any reason why a transistor inverters the input signal but not FET?

  2. Date: January 1, 2017 at 18:27
    Author: Dathan Walters

    The gates channel gets bigger when its overdriven pass the input level threshold causing the FETs source to drain channel is squeezed which the channel resistances goes up, this is what caused the 1dB gain compression?

  3. Date: January 2, 2017 at 22:01
    Author: Dathan Walters

    How about GAN, GaAs, LDMOS FET's, can you please explain about those too.

  4. Date: January 3, 2017 at 07:09
    Author: Dathan Walters

    The linearizers in RF power amplifiers are feedforward and Doherty topologies to reduce and IMD distortion by using phase shifting to cancel out the spectral regrowth and IMD.

  5. Date: January 7, 2017 at 07:06

    Hands down, this is the best explanation of basic FET operation that I've ever heard and I have a PhD in analog circuit design! Great great video. Made my day that this is available.

  6. Date: January 9, 2017 at 04:52
    Author: Dathan Walters

    Why are FETs are Unipolar and not bipolar? is it because the gate can't swing in the reverse polarity. A transistors base can have a positive and negative voltage cause of the biasing DC offset. Any reason why  you don't have to bias the gate to a Quiescent point/DC offset voltage?

  7. Date: January 20, 2017 at 04:23
    Author: Dathan Walters

    Is the FET's transconductance the Voltage Gain or Power Output of the FET? Why does a FET's gain and Power output wattage goes down over the years when used in a circuit like an amplifier.  When FETs are used in an amplifier, the amplifier will be rated 50watts full rated power but will degraded through the years and will be 40watts because the FET's transconductance and Power output wattage is lower.

  8. Date: January 27, 2017 at 04:14
    Author: Dathan Walters

    Are GAN, GaAs and LDMOS FET transistors sensitive to ESD and get damaged from ESD static voltages or only CMOS FET sensitive to ESD static voltages?

  9. Date: February 23, 2017 at 00:41
    Author: Dathan Walters

    Can you use Freeze cold spray on RF FET's like GaN, GaAs , LDMOS when trying to troubleshoot intermittent RF circuits? Will the Cold freeze spray damage the RF FET transistor devices?

  10. Date: February 23, 2017 at 02:13
    Author: Dathan Walters

    yes troubleshooting high wattage FET's 10watts to 500watt RF FET's, GaN, GaAs, LDMOS. The Freeze cold spray might fracture the device?

  11. Date: March 4, 2017 at 01:41
    Author: Dathan Walters

    When a FET is compress at P1dB which is "referenced to small signal gain". P1dB is 1dB less and referenced to small signal gain. P2dB is 2 dB's less and referenced to small signal gain. P3dB is 3 dB's less and referenced to small signal gain. Psat saturation is 1dB less from the maximum full rated power/wattage of the FET. Psat saturation is P6dB less and referenced to small signal gain. When a FET is in full rated power/watts or Max Pout of the FET, the FET is considered to be operating in it's Non-linear region?

  12. Date: March 18, 2017 at 03:17
    Author: Dathan Walters

    Why does a FET's gate current raise up when a FET is aged or has power/wattage degradation?

  13. Date: March 18, 2017 at 04:44
    Author: Dathan Walters

    When measuring a brand new FET's in an amplifier circuit gates resistance referenced to ground will be 500K and higher resistance. Measuring a used in an amplifier circuit FET's gate resistance referenced to ground will drop in resistance. The FET's gate impedance DC resistance has changed, any reason why?

  14. Date: March 30, 2017 at 00:07
    Author: Dathan Walters

    LDMOS FET's uses "Positive Voltage" on the gate, compared to GAN FET's and GaAs FET's uses "negative Voltage" on the gate. What is the advantage of using "negative voltage" compared to using "positive voltage" to bias the gate of a FET? The negative voltage FETs are always depletion mode FET's which have an advantage compared to enhancement mode FETs?

  15. Date: March 30, 2017 at 01:44
    Author: Dathan Walters

    So depletion mode FETs doesn't dissipate more heat, output higher wattage or have more electro carriers compared to enhancement mode FETs which are more linear, operate at a cooler temperature, output less wattage? Why would a designer choose a negative gate voltage compared to a positive gate voltage, what components in the circuit would decided this?

  16. Date: April 7, 2017 at 00:43
    Author: Dathan Walters

    If an RF amplifier's full rated power occurs at an input power level at -5dBm and the output power level was at 25watts. If I put a 5dB attenuator/Pi Pad on the input of the RF amplifier, full rated power will now occur at 0dBm and the output power level will be still at 25watts. The gain of the amplifier was at 44dBm/25watts, and the P1dB point compressed at 43dBm/20watts. When putting a 5dB attenuator on the front input port of the amplifier will change the gain of the amplifier from 44dBm minus 5dB =  39dBm/8watts. The new P1dB compression point is 1dB lower from 39dBm, which P1dB will be at 38dBm.  The full rated power stays the same but the P1dB compression point has changed, it's not relative. Why didn't P1dB compression point stay the same and compress at the same spot just 5dB's lower of gain?

  17. Date: April 8, 2017 at 00:29
    Author: Dathan Walters

    It seems that the if you add gain or take away gain of an amplifier, the P1dB will always stay the same. I thought that the P1dB was the "ratio or delta" of the input power level compared to the gain of the amplifier, this is not true. The P1dB is what the datasheet says the FET or Transistor device will occur at. If the amplifiers gain was 50dB, the FET or transistor will compress at the same point even if the amplifiers gain was 70dB. The amplifiers gain that is close to the P1dB compression point will have an input power level that is close to full rate power. If the amplifier compression point occurred at 51.8dBm/150 Watts with a Gain of 70dB, the input power level would be () 18.2 dBm. If the amplifiers gain was 65dB the input power level would be at () 13.2 dBm. If the Amplifier gain was at 60dB the input power level would be at () 8.2dBm. If the amplifiers gain was at 55dB the input power level would be at () 3.2dBm when the amplifier would compress 1dB lower. The Higher the Gain the earlier the amplifier will compress at 1dB, The lower the amplifiers gain, the later the amplifier will compress at 1dB.

  18. Date: May 15, 2017 at 09:20
    Author: Lyman Tsinnie

    What is meant when a device has a low or high input/output impedance..I see it everywhere but don't quite understand this impedance yet.. @w2aew

  19. Date: June 6, 2017 at 15:25
    Author: Moises BCSL

    Although it just an introduction to JFETs and MOSFETs its a great video. I always enjoy your videos. Nice work!!

  20. Date: June 12, 2017 at 09:44
    Author: Marty Harrison

    You make things look and make sense to all that view. pity I didn't have you as a teacher back in the day.

  21. Date: June 27, 2017 at 18:58

    In MOSFET, the gate is isolated from the channel, so it forms a capacitor. If we go to high frequencies, the impedance curve will change due to parasitic inductance (I am thinking of the video #56). What kind of interesting effects exist here because of the presence of semiconductors near this capacitor when the frequency increases?

  22. Date: July 21, 2017 at 02:01
    Author: waspinator

    What are some practical differences between a depletion MOSFET and a JFET?

  23. Date: August 6, 2017 at 20:35
    Author: mxm

    man i love u every thing make much more sense now .

  24. Date: August 14, 2017 at 22:32
    Author: Jan Heimann

    Best introduction on FETs that i've seen so far. Thanks a lot!

  25. Date: October 12, 2017 at 06:04

    Super clear explanations. Love the family tree. For somebody like me still figuring out what goes for what, it saved me alot of research. Thank you. Much appreciated

  26. Date: November 15, 2017 at 12:53
    Author: jonka1

    Beautifully made tutorial thank you.
    It interests me as a restorer of vintage stuff to note that the Jfet biasing is just like a vaccuum tube cathode bias method.

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